Patrol tour system

ABSTRACT

A patrol tour system for insuring that the tour station switches are operated in the proper sequence and within a predetermined amount of time by the guard making the tour which system comprises a common logic circuit for providing an indication of a delinquency in the time between the operation of the tour stations, an indication when the tour stations are operated out of a prescribed sequence, a tour in process indication, and a tour end indication, a status circuit having latching circuits connected to each of the tour station switches for prohibiting the repetitive reset of a common logic timing means by repetitive operation of only one of the tour station switches, and optionally a program circuit for establishing a predetermined sequence of operations of the tour stations.

United States Patent n 1 Rumpel [1 1 3,736,561 1 May 29,1973

[22] Filed:

[52] U.S. Cl. ..340/l47 P, 340/286, 340/306, 340/309.1, 340/312 [51]Int. Cl. ..G08b 25/00 I [58] Field of Search ..340/147 P, 223, 286,

Delbert 0. Rumpel, Mundelein, 111. I

Primary Exgminer ponald J. Yusko Att0rney Lamont B. Koontz and Trevor B.Joike ABSTRACT A patrol tour system for insuring that the tour stationswitches are operated in the proper sequence. and

within a predetermined amount of time by the guard making the tour whichsystem comprises a common logic circuit for providing an indication of adelinquency in the time between the operation of the tour stations, anindication when the tour stations are operated out of a prescribedsequence, a tour in process indication, and a tour end indication, astatus 287 circuit having latching circuits connected to each of thetour station switches for prohibiting the repetitive [56] ReferencesCited reset of a common logic timing means by repetitive UNITED STATESPATENTS operation of only one of the tour station switches, andoptionally a program circuit for establishing a 3,577,079 5/1971l-lorstmann ..340/306 X redetermined sequence of operations of the toursta- 3,579,221 5/1971 Ashley et a1. ..340/306 x 3,631,536 12/1971'Mosman ..340/286X H N 20 Claims, 7 Drawing Figures v PROCESSOR AND 4PRINTER l i IOO STATUS PROGRAM CKT CKT am A |2 Tut} -Tl3 I n5 889/8" DLQDISPLAY Q 30l- TH CIRCUIT 1 00s TOUR IN PROGRESS PATENTEUMAYZQ I9753,736,561

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PATENTEI] MAY 29 I975 sum u [IF 4 mwwmoomm Z. mDOk NOT I This inventioninvolves a fire and/or security patrol system. The philosophy behindsuch a system is to insure that a guard, who is assigned the task ofinvestigating predetermined locations, i.e., stations, within a buildingto insure that such locations are free from fire and in a securedstatus, properly conducts his tour (investigation).

To acknowledge that the guard has investigated the stations, a keyswitch is positioned at each tour station which the guard is toinvestigate. As the guard actuates the key switch, a latching circuit isoperated such that further actuation of the switch will not affect therest of the .tour system. When the latching circuit is operated, a timeris reset. If the timer were not reset, i.e., were allowed to time out, adelinquency signal is provided on appropriate display apparatus. Thetimer would not be reset if the guard failed to operate a tour stationswitch within the prescribed amount of time.

The system is designed to operate with or without a program according toa prescribed sequence. If the system is to be operated'without aprogram, the prescribed sequence is such that the guard must operate thefirst station first and the last station last. The intermediary stationscan be operated in any sequence whatsoever. Upon the operation of thefirst station first, a tour in progress signal is provided on thedisplay apparatus. If the first station is not operated first, this tourin progress signal is not provided. If the last station is not operatedlast, an out of sequence signal is provided.

With the use of a program, however, the prescribed sequence in which thestations are to be operated can be established according to a programand in any predetermined manner and, should any station be operated outof the prescribed sequence, an out of "sequence signal is provided.

Furthermore, the outputs from the latching circuits are optionallyconnected to a processor and printer. The processor and printer can, forinstance, provide a print out as each station is operated or a printoutof a log of all stations which have been operated whenever an out ofsequence or a delinquency has occurred.

The patrol tour system collects all of the information without use of amemory at the central station. In this manner, the printer or displayapparatus need only indicate the occurrence of a delinquency or an outof sequence operation.

These and other features will be seen more clearly in the followingdetailed description of the drawings in which:

FIG. 1 is a block diagram of the patrol tour system.

FIG. 2 isa detailed schematic of the status circuit.

FIG. 3 is a detailed schematic of the program circuit.

FIG. 4 is a detailed schematic diagram of the common logic circuit.

FIG. 5 is a circuit diagram of the optical isolator used in the circuitsof FIGS. 2 and 3.

FIG. 6 is a detailed representation of the counter and decoder used inthe circuit of FIG. 4.

FIG. 7 is a block diagram showing how the patrol tour system can bemated with a data gathering system;

In FIG. 1, switches 1-10 represent the key switches located at the tourstations to be investigated by the patrolling guard. These switches areconnected to the status card such that as each one of the switches isoperated a signal is provided at terminal T12 which is con-' nected tothe common logic circuit '101 to reset a timing apparatus within thelogic circuit. A

Reference numerals T1'T15 are used throughout the schematics to'show thecommon connections between the circuits of FIGS. 2-4.

If aprogram circuit is used, the status switches 1-10 are connectedthrough the status circuit to the program circuit. The program circuit201 establishes the sequence in which stations 1-10 must be operated bythe guard. When the first station which is programmed number 1 by theprogram circuit is operated, an output signal appears at terminal T13which is connected to the common logic circuit to provide a tour inprogress signal to the display apparatus 301. If any of the stations ll0are operated out of the sequence established by the program circuit, anoutput signal is produced at terminal Tl4'whichis connected'to thecommon logic circuit for providing an out of sequence signal (008) tothe display apparatus 301'.

The timing circuit located within the common logic circuit establishes apredetermined amount of time within which each tour station must beoperated. If the time between operation of any two "stations'l-loexceeds the time preset by the timing circuit of the common logiccircuit 101, a delinquency signal (DLQ) is provided by the common logiccircuit to the display apparatus 301.

The operation and manner of use of the circuit show in FIG. 1 is asfollows:

The key switches 1-10 are positioned at those locations, e.g., rooms orareas, of a building to be investigated by a guard'to insure that suchlocations are secured and free from fire. The remainder of the circuitshown in FIG. 1 is located at a central location within the building.Assuming that'the proper sequence of operation of the key switches 1'l0is in the numerical order ll0, the guard will proceed to conduct histour at the proper time. Upon arrival at the first location, the guardwill operate key switch 1 which causes a circuit in the status circuit'1 l'to latch. The latching of this circuit provides two functions. Thefirst is to reset the delinquency timer apparatus of the common logiccircuit 101. The second function is to use this latching output todetermine if the stations are in the proper sequence. If a programcardis used, this second function is provided by an output signal from thestatus circuit to the program circuit 201.

Upon operation of station number 1, the status circuitlatching meanswill provide an output to the program circuit 201. This output is usedto provide an output from program circuit 201'to terminal T13. Thissignal is then supplied to the common logic circuit 101 to provide thetour in progress signalto the display apparatus 301.

After the timer in the common logic 101 has been reset, it begins a newtiming'operation. The guard then proceeds to location number 2. If thetimer apparatus in the common logic circuit 101 times out before theguard reaches station number 2,,a delinquency signal is provided to thedisplay apparatus 301. However, if the guard reaches station number 2and operated its associated key switch within the time allotted him bythe timing circuit in the common logic circuit 101, the correspondinglatching circuit in the status circuit 1 1 is op-' erated toreset thetimer of the common logic circuit 101 and to provide an output to theprogram circuit If the guard omits station number 3 in his tour andinstead proceeds to station number 4 and operates the key switch there,the latching circuit, associated with station 4, in the status circuit11 will be operated to reset the timer apparatus in the common logiccircuit 101. However, the latching of this circuit will also provide anoutput to the program circuit 201 which will sense the failure tooperate station 3 in its prescribed sequence. As a result, the programcircuit 201 will provide an output on terminal T14 to the common logiccircuit 101 to provide a delinquency output to display apparatus 301.

Upon proper operation of stations 1-10 by the guard making his tour, theoperation of the last station will cause status circuit 11 to provide anoutput on terminal T11 which is supplied to the common logic circuit 101to provide a reset circuit signal. This reset circuit signal is suppliedfrom the common logic circuit 101 to terminal T15 and then to the statuscircuit 11 to reset all of the latching circuits contained therein. Atthis point, the circuit is ready for the guard to begin a new tour.

When discussing the details of the status circuit 11, the common logiccircuit 101 and the program circuit 201, reference numerals Tl-T15 areredundantly used throughout these three circuits to show the commonconnections between the circuits of FIGS. 2-4.

STATUS CIRCUIT FIG. 2 shows in more detail thestatus circuit 11 shown inblock form in FIG. 1. A positive terminal of battery 12 is connected tothe movable contacts of tour station switches 1-10 the stationarycontacts of which are connected to one of the input lines of theirrespective optical isolators 21-30. The other input line to opticalisolators 21-30 are all connected together and to the negative terminalof battery 12.

FIG. 5 shows the optical isolator which comprises a light emitting diode31 and a light responsive transistor 32. When the diode 31 is suppliedwith current, it gives off light which causes the transistor 32 toconduct. When placed in one of the boxes 21-30 of FIG. 2, the lightemitting diode is connected between the input lines from the switches1-10 and battery 12 and the collector emitter circuit of the transistoris connected between the output line and the ground terminal which isshown in FIG. 2. The output lines 21-30' from optical isolators 21-30are connected to respective latching circuits 41-50.

Each latching circuit comprises two interconnected Nand gates whoseoutput is normally low and which goes high upon the application of a lowsignal to their respective input terminals 41-50'. Each output line21"-30' is connected to a +V source through a respective resistor 51-60.Thus, when the transistor and the optical isolator is de-energized, theinputs 4150 to latches 41-50 are normally in a high condition such thatthe outputs from these latches are normally in a low condition.

The outputs from latches 41-50 are directly connected to terminalsT1-T10 which are connected to input terminals T1-T10 of FIG. 3 andterminals T1-Tl0 of FIG. 4.

Additionally, the outputs from latches 41-50 are connected" throughcapacitors 61-70 and inverters 71-80, respectively, to an outputterminal T12. Resistors 81-90 are connected from the junctions of theirrespective capacitors 61-70 and inverters 71-80 to ground. Thecapacitors function to give a short pulse on terminal T12 whenever oneof the outputs from latching circuits 41-50 go high. As will be seenhereinafter, a pulse on terminal T12 resets the timing apparatus of thecommon logic circuits 101.

As can be seen from FIGS. 1 and 2, the output from latches 41-50 arealso connected through inverters 91-100 to the processor and printerapparatus 401.

PROGRAM CIRCUIT FIG. 3 shows the program circuit which can be used withthe disclosed patrol tour system. If it is desired to operate the systemwithout a program, then the prescribed sequence becomes such that thefirst station must be operated first, the last station must be operatedlast, and the intermediary stations can be operated in any sequencewhatsoever. However, when using a program circuit, either of two programcircuits can be used depending upon the position of switch 202. Thus,two different sequences can beestablished for the patrol tour system. Ifthe switch 202 is closed on stationary contact 203, the program circuitshown in FIG. 3 is selected. However, if the switch 202 is in an upperposition against stationary contact 204, the other program circuit, notshown, is selected. The other program circuit is merely connected inparallel to the one shown in FIG. 3. If it is desired to have the guardoperate the stations according to the program established by the circuitof FIG. 3, switch 202 is closed upon stationary contact 203. The battery205, thereby, supplies current through resistor 206 to the opticalisolator 207 and back to the negative terminal of battery 205 throughdiode 208. Connected between the inputs lines to optical isolator 207 isa resistor 209 and a capacitor 210.

With no current being supplied to the optical isolator, the isolator, asshown in FIG. 5, emits no light from the diode 31 and, therefore, thetransistor 32 is nonconducting such that the inverter 21 1, because itsinput is connected through a resistor 212 to a +V source, presents a lowsignal to input lines 213 and 214 of Nand gates 215 and 216respectively. With a low signal on the inputs 213 and 214, the Nandgates 215 and 216 I are inhibited from providing a low signal onterminals T13 and T14. Regardless of the signal applied to terminal T1,the terminals T13 and T14 will have a high output.

Terminal T1 is connected from station contact 1 by a jumper 232 tosequence contact 1 which in turn is connected to the other input 217 ofNand circuit 215. Also, terminal T1 is connected through inverter 219 toinput 220 of Nand gate 221. Terminal T2 is shown connected to inputterminal 222 of Nand gate 221 and also through inverter 223to inputterminal 224 of N and circuit 225.

Terminal T3 is shown connected to input terminal 226 of Nand gate 225and will be connected through an inverter to the next Nand circuit (notshown) and so on for each of the input terminals. Terminal T9 isconnected to the input of the preceding Nand gate (not shown) and isalso connected through an inverter 227 to the input 228 of Nand gate229. Terminal T10 is connected directly to input 230 of Nand circuit229.

Although FIG. 3 is shown such that the station contacts 1-10 aredirectly jumpered to their respective sequence contacts 1-10, it canreadily be seen .that the jumpers can be arranged in any desired manner.The manner in which the station contacts are jumpered to the sequencecontacts will determine the tour sequence that the guard is to follow.Thus, the station contact 1 can be connected to sequence contact if itis desired to operate station number 1 as the last station in thesequence. If it is desired to operate station 10 as the first station inthe sequence, station contact 10 will be jumpered to sequence contact 1.

COMMON LOGIC CIRCUIT FIG. 4 shows the common logic circuit shown'inblock diagram form of FIG. 1. The same terminal numbers have been usedto indicate the manner in which the common logic circuit is to beconnected to the status circuit of FIG. 2 and the program circuit shownin FIG. 3.

When the guard begins his tour and assuming that a program circuit isnot used (when a program circuit is used, terminals T16 and T17 shown inFIG. 4 are grounded) the operation of key switch 1, representing the keyswitch of the first station, causes input 41' (FIG. 2) to go low whichdrives the output from latch 41 (FIG. 2) high. This high is connected toterminal T1 of FIG. 2 and, as shown in FIG. 4, back biases diode 111which presents a high to the input of Nand gate 102. Since the otherterminal of the Nand gate is connected through a resistor 103 to asource, the output of the Nand gate goes low which drives the output ofinverter 104 high which drives the output of Nand gate 105 (acting as aninverter) low energizing relay coil 106 to pull in relay contacts 107 toprovide a tour in progress signal. The tour in progress signal may beused to energize a tour in progress light, or it may be used to providea signal to the processor and printerto print out a patrol tour startsignal.

Also, when the'output from latch 41 of the status circuit goes high, amomentary signal is applied by capacitor 61 and inverted by inverter 71and applied to terminal T12. This signal is a momentary low which isconnected through the terminal T12 of FIG. 4 (the common logic circuit)to a one shot circuit 108. The inverted terminal of the one shot isutilized to reset the counter and decoder 109, the reset latch 110 andto discharge capacitor 121.

When the inverted terminal of the one shot 108 again goes high, thecapacitor 121 is allowed to charge from the +V source through resistor122, resistor 123 and to ground. The capacitor is connected to one inputterminal of PUT 124, the other input terminal of which is connected to avoltage divider 125 and 126 connected between the +V source and ground.The +V source is also connected through a resistor 127 to the emitter oftransistor 128 the collector which is connected to ground. The junctionof resistors 125 and 126 is connected through a resistor 129 to the baseof transistor 128. When the charge on capacitor 121 reaches 0.6 voltabove the voltage established by the junction of resistors 125 and 126,the capacitor discharges through the PUT 124 which momentarily pullsdown the voltage at junction A which applies a pulse to transistor 129momentarily turning it off. The output from the transistor is used tostep the counter and decoder 109.

The outputs from the counter and decoder are connected to terminals 130which provide for 3 minute, 6 minute, 9 minute, l2 minute, minute or 18minute time intervals. A jumper 131 is used to select the time duringwhich a guard is required to operate the stations in his tour. As shown,a 15 minute interval is chosen.

Should the guard fail to energize the proper station in the sequencewithin 15 minutes, the capacitor 121 will have charged and'discharged asufficient number of times to step the counter around to a positionwhere it provides an output through jumper 131 to latch circuit 132which presents a high to the input of Nand gate 133 which causes relay134 to be energized closing contacts 135 to present a delinquency signalon the output of terminals T18 and T19. These terminals T18 and T19 maybe directly connected to a light to provide a delinquency signal or maybe connected to the proces sor and printer apparatus for providing aprint out of a delinquency.

However, if the guard operates station 2, for instance, within the 15minute time interval, latching circuit 42 (FIG. 2) presents a high onits output which. is connected through capacitor 62 and inverter 72 topresent a momentary low signal on terminal T12. As shown in FIG. 4, amomentary low on T12 will energize the one shot 108 to dischargecapacitor 121, to reset the counter and decoder 109 to a 0 count. As theguard operates each station within the predetermined amount of time(i.e., 15 minutes) the one shot 108 will repetively reset the timer andthe counter and decoder circuit 109 such that relay coil 134 remainsde-energized.

It is to be noted that the output terminals T1 and T10 of the statuscircuit of FIG. 2 are connected to the diodes 111-120 of FIG. 4. Sinceterminals T1-T10 of the status circuit (FIG. 2) are normally low, theoutput from all the diodes will be low until all diodes 1 ll12 0 areback biased. When all stations have been operated, terminal B of FIG. 4will go high which presents, through a time delay capacitor 136, a highto the input of inverter 137 which drives the input to inverter 138 lowwhich presents a high to one of the inputs of Nand circuit 139.

Upon closure of station switch 10, the last station, latch 50 of thestatus circuit will provide a low signal on terminal T11 which, as shownin FIG. 4 (common logic circuit), will present a high on the output ofinverter 140 which is connected through a time delay capacitor 141 toone of the inputs to Nand circuit 142. In addition, inverter 140presents a high to a second input of Nand circuit 139. Furthermore, whenlatch 50 shown in FIG. 2 is tripped, terminal T12 is presented with amomentary low which energizes one shot 108 to provide a momentary low tothe third input of Nand circuit 139. It is noted that the output fromone shot 108 is normally high and will, after a predetermined time froma low signal applied to terminal T12 go back to a high status. Thesignal coming from diodes 111-120 and from terminal T11, by virtue ofcapacitors 136 and 141, are time delayed so that a high is ap plied tothe inputs of Nand gate 139 when the output of one shot 108 goes backhigh. A high on all inputs of Nand 139, which results from all tourstations having been operated and from the operation of the laststation, presents a low to the input of latching circuit 143 whichpresents a high to one of the-inputs of Nand gate 144 the other input ofwhich is always high due to its connection through a resistor 145 to the+V source. The output of Nand 144 therefore goes low which energizes aone shot circuit 146. The non-inverting input of one shot 146 operatesparallel Nand circuit 147 to present a signal on terminal T15 which, asshown in the status circuit (FIG. 2), will reset all latches 41-50. Thisunlatching of latches 41-50 occurs when the proper sequence has beencarried out.

However, assume that station 10, the last station, is operated beforeone of the previous stations, e.g., station 9, is operated. Outputterminal B from diodes 111-120 will be low which causes the output frominverter 137 to be high which is applied to one of the input terminalsof Nand 142. Also, the closure of switch 10 results in a low beingapplied to'terminal T11 (status circuit to the common logic circuit)which drives the output of inverter 140 high which is connected to theother input of Nand circuit 142. With both inputs being high, a low ispresented at the output of Nand 142 which causes the output of inverter148 to go high. When the output of inverter 148 goes high, a high ispresented to one input terminal of Nand gate 149 the other inputterminal of which is high because it is connected through resistor 150to the +V source. When both input terminals of Nand gate 149 are high,the output goes low which drives the output of inverter 151 high whichdrives the output of Nand gate 152 low. The relay 153 is thus energizedto close contacts 154 to provide an out of sequence signal on terminalsT20 and T21 which may be connected to a light on the display apparatusor may be connected to the processor and printing apparatus to providean out of sequence print out.

It is noted that stations 2-9 may be operated in any sequence whatsoeveras long as the first station is operated first and the last station isoperated last. When all stations 1-10 are operated and the last stationis operated last, the terminal B is presented with a high signal whichcauses a low signal on the output of 137 which is connected to one ofthe inputs of Nand 142 which inhibits the out of' sequence signallingcircuit.

When a program circuit is used, terminals T17 and T16 of FIG. 4 aregrounded. The grounding of terminal T16 prohibits energization of Nandgate 102 and the grounding of terminal T17 inhibits the output frominverter 148 such that the out of sequence signal must now come fromterminal T14 originating at the program circuit. When using the programcircuit as shown in FIG. 3 and with the jumpers as shown, the closure ofswitch 202 to stationary contact 203 results in a high signal beingplaced on inputs 213 and 214 of Nand gates 215 and 216 respectively.When the station 1 switch is closed, latching circuit 41 presents a highon its output which is connected through terminal T1 and applies a highto the other input terminal of Nand gate 215 (FIG. 3) which causes theoutput of that Nand gate to go low. A low on T13 results in a high onthe output of inverter 104 (FIG. 4) which results in a low from theoutput of Nand gate 105 which energizes relay 106 closing contacts 107to provide the tour in progress signal. Also, a high on terminal T1(FIG. 3) results in a low from the output of inverter 219 which inhibitsthe operation of Nand gate 221. Normally, the output from the inverters219, 223, and 227 are high such that if, for instance, station T10 wereoperated before station 9, a 1 would appear on both inputs 228 and 230of Nand gate 229 which will result in a low on the output bus connectedto the outputs of Nand gates 221, 225 and 229. A low on any one of theoutputs of these Nand gates result in the whole bus going low whichresults in the output from inverter 231 going high which causes terminalT14 to go low. This low on terminal T14, as shown in FIG. 4, is appliedto the input of inverter 151 causing its output to go high which causesthe output of Nand gate 152 to go low energizing relay 153 to closecontacts 154 to provide the out of sequence signal on terminals T20 andT21.

However, if all stations are operated in the proper sequence, each timea station is energized, the inverted input to the corresponding Nandgate 221, 225 or 229 will go low inhibiting the change in the outputfrom that Nand gate as the subsequent station is operated. Since theinput to inverter 231 is normally high and the output from the inverteris normally low, the output of Nand gate 216 is prohibited from changingits state.

In FIG. 6, the counter and decoder 109 comprises two counters 501 and502 and Nand circuits 503, 504, 505, 506, 507 and 508. The outputs fromthe Nand gates are connected to the terminals for providing timedurations from 3 minutes to 18 minutes in increments of 3 minutes each.Once the two counters have been reset, a 0 appears on all outputs. Whenthe first pulse arrives from the timing circuit in the common logiccircuit of FIG. 4, a 1 appears on the Q1 output of counter 501. However,it can be seen from FIG. 6 that this 1 will not change the states of anyof the Nand circuits. Upon the next pulse being received bycounter 501,O1 goes to 0 and Q2 has a 1 on its output. Again, this arrangement isinsufficient to provide an output from any of the Nand circuits.However, when the next pulse is received to counter 501, output 01 goeshigh which presents two ls on the input of Nand circuit 503 driving itsoutput low which, if the 3 minute terminals are jumpered, drives theoutput of latch 1 10 high which pulls the output of Nand circuit 133 lowto energize the relay. If the jumper is not across the 3 minuteterminals, the counter continues counting until either it reaches theproper jumper terminals or it is reset.

FIG. 7 shows how the patrol tour system may be used in a data gatheringsystem such as the Honeywell DELTA 2000. Instead of using the displayapparatus 301 as shown in FIG. 1, the outputs from the patrol toursystem are fed into an interface apparatus 402 which is designed toconvert the information supplied from the patrol tour system by way oflines 411-420 from the inverters 91-100 shown in FIG. 1 into binarycoded form. In addition lines 403-405, corresponding to the delinquencysignal, tour in progress signal and out of sequence signal shown in FIG.1 are fed from the patrol tour system to the interface apparatus.

The interface apparatus is connected to a transceiver apparatus 406 fortransmitting binary coded messages to the central station 407 by way ofa coax transmission line 408. The central station comprises atransceiver 409 adapted to receive the messages coming in over line 408and supplying the messages to a processor apparatus 421 for display on aprinter 422.

The manner in which generally the messages are constructed and theoperation of the data gathering system are shown in copendingapplication Ser. No. l78,095 filed Sept. 7, 1971. The manner in whichthe printer apparatus receives the messages and provides a print outdisplay is shown in U.S. Pat. No. 3,618,026.

The central station 407 may be programmed to provide a print out as eachtour station is operated or may give a print out of only the start ofthe tour, the end of the tour, a delinquency and an out of sequenceindication. Alternatively, the printer may print out a log of allstations operated whenever a delinquency has occurred as well as thestart of the tour and the end of the tour.

The embodiments of the invention in which an exclusive property or rightis claimed are defined as follows:

1. A patrol tour system having a plurality of stations to be operated ina prescribed sequence, the system comprising:

status circuit means having a latching means for each of said stationswhereby the latching means is latched upon operation of its associatedstation;

delinquency reset means connected to said latching means for providing adelinquency reset signal each time one of said latching means islatched;

logic circuit means having timing means for providing a delinquencysignal upon the lapse of a predetermined time, said logic circuit meansbeing responsive to each of said delinquency reset signals for resettingsaid timing means upon the receipt of said delinquency reset signals,said logic circuit further having out of sequence sensing means forproviding an out of sequence signal whenever said stations are operatedout of said prescribed sequence; and

display apparatus responsive to said delinquency signal and said out ofsequence signal for providing a delinquency alarm and an out of sequencealarm respectively.

2. The system of claim 1 wherein said system further comprises a programmeans connected to said latching means and to said logic circuit meansfor establishing a predetermined sequence in which said station must beoperated.

3. The system of claim 2 wherein said program means comprises at leasttwo programs and means to select the particular sequence in which thestations must be operated.

4. The system of claim 3 wherein said program means includes means forproviding a program out of sequence signal when said stations have beenoperated out of theprogram sequence, and said logic circuit meansincluding means responsive to said program out of sequence signal forproviding said out of sequence signal.

5. The system of claim 1 wherein said timing means comprises a timerapparatus for providing periodic pulses, a counter means connected tosaid timer apparatus for receiving said pulses and a decoder connectedto said counter for decoding the output of said counter into a pluralityof time durations.

6. The system of claim 5 wherein said logic means further compriseslatch reset means responsive to the operation of all of said stationsand to said last station for resetting the latching means.

7. The system of claim 6 wherein said status means includes means forproviding a last station signal, said logic circuit means includes meansresponsive to the latching means for providing a signal when allstations have been operated, and said logic circuit means furtherincludes means responsive to said last station signal and to said signalprovided when all stations have been operated for providing said out ofsequence signal.

8. The system of claim 6 further comprising a program means connected tosaid latching means and to said logic circuit means for establishing apredeter mined sequence in which the stations must be operated.

9. The system of claim 8 wherein said program means comprises at leasttwo programs and selection means to select the particular sequence inwhich the stations must be operated.

10. The system of claim 1 wherein said status circuit means, saiddelinquency reset means and said logic circuit means are located at aremote area and transmit their information in binary coded form over achannel to a central station for display. 1 i I 1 1. A patrol toursystem having a plurality of stations to be operated in a prescribedsequence, the system comprising;

status circuit means having a latching means for each of said stationswhereby the latching means is latched upon operation of its associatedstation;

delinquency reset means connected to said latching means for providing adelinquency reset signal each time one of said latching means islatched;

logic circuit means'having timing means for providing a delinquencysignal upon the lapse of a predetermined time between operation of saidstations, said timing means being reset upon the receipt of saiddelinquency reset signal, said logic circuit further having out ofsequence sensing means for providing an out of sequence signal wheneversaid stations are operated out of said prescribed sequence; and

display apparatus consisting of a first means responsive to theoperation of the first station for providing a patrol tour start signal,a second means responsive to the operation of said last station forproviding a tour end signal, a third means responsive to saiddelinquency signal for providing a delinquency indication, and a fourthmeans responsive to said out of sequence signal for providing an out ofsequence indication, whereby only indications of the patrol tour start,tour end, delinquency and out of sequence are given.

12. The system of claim 11 wherein said system further comprises aprogram means connected to said latching means and to said logic circuitmeans for establishing a predetermined sequence in which said stationsmust be operated.

13. The system of claim 12 wherein said program means comprises at leasttwo programs and means to select the particular sequence in which thestations mustbe operated.

14. The system of claim 13 wherein said program means includes means forproviding a program out of sequence signal when said stations have beenoperated out of sequence, and said logic circuit means including meansresponsive to said program out of sequence signal for providing said outof sequence signal.

15. The system of claim 11 wherein said timing means comprisesa timerapparatus for providing periodic pulses, a counter means connected tosaid timer apparatus for receiving said pulses and a decoder connectedto said counter for decoding the output of said counter into a pluralityof time durations.

16. The system of claim 15 wherein-said logic means further compriseslatch reset means responsive to the operation of all of said stationsand to said last station for resetting the latching circuit means. i

17. The systemof claim 16 wherein said status means includes means forproviding a last station signal, said logic circuit means includes meansresponsive to the latching circuit means for providing a signal when allstations have been operated, and said logic circuit means furtherincludes means responsive to said last means comprises at least twoprograms and selection means to select the particular sequence in whichthe stations must be operated.

20. The system of claim 1 1 wherein said status circuit means, saiddelinquency reset means and said logic circuit means are located at aremote area and transmit their information in binary coded form over achannel to a central station for display.

a i I I OI

1. A patrol tour system having a plurality of stations to be operated ina prescribed sequence, the system comprising: status circuit meanshaving a latching means for each of said stations whereby the latchingmeans is latched upon operation of its associated station; delinquencyreset means connected to said latching means for providing a delinquencyreset signal each time one of said latching means is latched; logiccircuit means having timing means for providing a delinquency signalupon the lapse of a predetermined time, said logic circuit means beingresponsive to each of said delinquency reset signals for resetting saidtiming means upon the receipt of said delinquency reset signals, saidlogic circuit further having out of sequence sensing means for providingan out of sequence signal whenever said stations are operated out ofsaid prescribed sequence; and display apparatus responsive to saiddelinquency signal and said out of sequence signal for providing adelinquency alarm and an out of sequence alarm respectively.
 2. Thesystem of claim 1 wherein said system further comprises a program meansconnected to said latching means and to said logic circuit means forestablishing a predetermined sequence in which said station must beoperated.
 3. The system of claim 2 wherein said program means comprisesat least two programs and means to select the particular sequence inwhich the stations must be operated.
 4. The system of claim 3 whereinsaid program means includes means for providing a program out ofsequence signal when said stations have been operated out of the programsequence, and said logic circuit means including means responsive tosaid program out of sequence signal for providing said out of sequencesignal.
 5. The system of claim 1 wherein said timing means comprises atimer apparatus for providing periodic pulses, a counter means connectedto said timer apparatus for receiving said pulses and a decoderconnected to said counter for decoding the output of said counter into aplurality of time durations.
 6. The system of claim 5 wherein said logicmeans further comprises latch reset means responsive to the operation ofall of said stations and to said last station for resetting the latchingmeans.
 7. The system of claim 6 wherein said status means includes meansfor Providing a last station signal, said logic circuit means includesmeans responsive to the latching means for providing a signal when allstations have been operated, and said logic circuit means furtherincludes means responsive to said last station signal and to said signalprovided when all stations have been operated for providing said out ofsequence signal.
 8. The system of claim 6 further comprising a programmeans connected to said latching means and to said logic circuit meansfor establishing a predetermined sequence in which the stations must beoperated.
 9. The system of claim 8 wherein said program means comprisesat least two programs and selection means to select the particularsequence in which the stations must be operated.
 10. The system of claim1 wherein said status circuit means, said delinquency reset means andsaid logic circuit means are located at a remote area and transmit theirinformation in binary coded form over a channel to a central station fordisplay.
 11. A patrol tour system having a plurality of stations to beoperated in a prescribed sequence, the system comprising; status circuitmeans having a latching means for each of said stations whereby thelatching means is latched upon operation of its associated station;delinquency reset means connected to said latching means for providing adelinquency reset signal each time one of said latching means islatched; logic circuit means having timing means for providing adelinquency signal upon the lapse of a predetermined time betweenoperation of said stations, said timing means being reset upon thereceipt of said delinquency reset signal, said logic circuit furtherhaving out of sequence sensing means for providing an out of sequencesignal whenever said stations are operated out of said prescribedsequence; and display apparatus consisting of a first means responsiveto the operation of the first station for providing a patrol tour startsignal, a second means responsive to the operation of said last stationfor providing a tour end signal, a third means responsive to saiddelinquency signal for providing a delinquency indication, and a fourthmeans responsive to said out of sequence signal for providing an out ofsequence indication, whereby only indications of the patrol tour start,tour end, delinquency and out of sequence are given.
 12. The system ofclaim 11 wherein said system further comprises a program means connectedto said latching means and to said logic circuit means for establishinga predetermined sequence in which said stations must be operated. 13.The system of claim 12 wherein said program means comprises at least twoprograms and means to select the particular sequence in which thestations must be operated.
 14. The system of claim 13 wherein saidprogram means includes means for providing a program out of sequencesignal when said stations have been operated out of sequence, and saidlogic circuit means including means responsive to said program out ofsequence signal for providing said out of sequence signal.
 15. Thesystem of claim 11 wherein said timing means comprises a timer apparatusfor providing periodic pulses, a counter means connected to said timerapparatus for receiving said pulses and a decoder connected to saidcounter for decoding the output of said counter into a plurality of timedurations.
 16. The system of claim 15 wherein said logic means furthercomprises latch reset means responsive to the operation of all of saidstations and to said last station for resetting the latching circuitmeans.
 17. The system of claim 16 wherein said status means includesmeans for providing a last station signal, said logic circuit meansincludes means responsive to the latching circuit means for providing asignal when all stations have been operated, and said logic circuitmeans further includes means responsive to said last station signal andto said signal provided when all stations have been operated forproviding sAid out of sequence signal.
 18. The system of claim 16further comprising a program means connected to said latching means andto said logic circuit means for establishing a predetermined sequence inwhich the stations must be operated.
 19. The system of claim 18 whereinsaid program means comprises at least two programs and selection meansto select the particular sequence in which the stations must beoperated.
 20. The system of claim 11 wherein said status circuit means,said delinquency reset means and said logic circuit means are located ata remote area and transmit their information in binary coded form over achannel to a central station for display.